This invention relates to a clock generator employing a circuit known as a phase locked loop (PLL).
As microprocessors and microcontrollers incorporating IC's increase their operating frequency to 40 MHz and more, it is necessary to eliminate what is known in the art as clock skew, i.e., the delay between an external clock signal and an internal clock signal caused by a clock driver. From the viewpoint of system designs, for optimum performance, it is most advantageous to increase only the frequency of an internal clock signal, without increasing the frequency of an external clock signal. Therefore, clock generators employing a PLL have been commanding attention recently.
FIG. 12 shows a conventional clock generator with a PLL. Such a clock generator produces an internal clock signal whose frequency is twice that of an external clock signal. A phase detector 10 makes a comparison in phase between a reference clock signal 40 fed from the outside and a feedback clock signal 32 as a result of dividing the frequency of an internal clock signal 34 with a frequency twice that of the reference clock signal 40. The phase detector 10 then delivers to a loop filter 14 a signal proportional to a phase difference obtained by the comparison via a charge pump 12 in which the signal is converted into a voltage value proportional to the phase difference. With this voltage as a control voltage, a voltage-controlled oscillator (VCO) 16 produces a signal whose frequency is four times that of the reference clock signal 40. The VCO 16 is followed by a first divide-by-two 18, i.e., a frequency divider which is fed with an oscillation output delivered from the VCO 16 and produces; a 50% duty ratio signal with a frequency twice that of the reference clock signal 40 for driving a load circuit via a clock driver 21. The internal clock signal 34 which is an output signal of the clock driver 21 is further frequency-divided by two by a second divide-by-two 24 to become the feedback clock signal 32.
In accordance with the PLL described above, clock skew is reduced to a minimum by producing the internal clock signal 34 at a frequency twice that of the reference clock signal 40 and by synchronizing the reference clock signal 40 and the internal clock signal 34. An example of this type of clock generators is disclosed by I. A. Young et al in the paper entitled "A PLL Clock Generator with 5 to 110 MHz Lock Range for Microprocessors", ISSCC, DIGEST OF TECHNICAL PAPERS, pp. 50-51, Feb. 1992.
The foregoing techniques, however, have several disadvantages. For example, it is not possible to start clocking of the internal clock signal 34 at a particular phase. Additionally, it is not possible to interrupt such clocking at a particular phase.
In other words, at the time when the feed of the reference clock signal 40 to a PLL starts, the lock-in time necessary for the internal clock signal 34 to fall in synchronism with the reference clock signal 40 is required. During the duration of the lock-in time, the unauthorized internal clock signal 34, which is asynchronous with the reference clock signal 40, will have been fed to every lead circuit in IC's.
Further, if the feed of the reference clock signal 40 to a PLL is brought to a halt so as to interrupt the feed of the internal clock signal 34, this makes the phase detector 10 unable to function normally. The entire PLL is no longer in a phase-synchronization status, that is, the status of being locked-in. Disadvantageously, this results in the provisional feed of the internal clock signal 34 asynchronous with the reference clock signal 40 to the lead circuit. The restarting of clocking requires the lock-in time again. Likewise, the unauthorized internal clock signal 34, which is asynchronous with the reference clock signal 40, will have been fed to the lead circuit. Accordingly, it is not possible to momentarily restart the feed of the internal clock signal 34 at a cycle right after another at which the feed of the reference clock signal 40 comes to a stop.
Techniques for interrupting the internal clock signal 34 at any particular phase and restarting its clocking at any particular phase have beneficial effect on, for example, step execution and the interruption/restart of operation at the time of debugging in systems (both hardware and software) employing IC's, and further such techniques find applications in controlling clock signals for the management of power consumption in systems and IC's. However, due to the existence of lock-in time, it is not possible to learn the actual start/restart timing of clocking from the outside of an IC. This presents such a problem that the application/cancellation timing of a system reset signal cannot be fixed in a unique way.